This book is a summary of more than a decade of research in the area of backend optimization. It contains the latest fundamental research results in this field. While existing books are often more oriented toward Masters students, this book is aimed more towards professors and researchers as it contains more advanced subjects.
It is unique in the sense that it contains information that has not previously been covered by other books in the field, with chapters on phase ordering in optimizing compilation; register saturation in instruction level parallelism; code size reduction for software pipelining; memory hierarchy effects and instruction level parallelism.
Other chapters provide the latest research results in well-known topics such as register need, and software pipelining and periodic register allocation.
Part 1: Prolog: Optimizing Compilation
Chapter 1 On the Decidability of Phase Ordering in Optimizing Compilation
Part 2: Instruction Scheduling
Chapter 2 Instruction Scheduling Problems and Overview
Chapter 3 Applications of Machine Scheduling to Instruction Scheduling
Chapter 4 Instruction Scheduling Before Register Allocation
Chapter 5 Instruction Scheduling After Register Allocation
Chapter 6 Dealing in Practice with Memory Hierarchy Effects and Instruction Level Parallelism
Part 3: Register Optimization
Chapter 7 The Register Need of a Fixed Instruction Schedule
Chapter 8 The Register Saturation
Chapter 9 Spill Code Reduction
Chapter 10 Exploiting the Register Access Delays Before Instruction Scheduling
Chapter 11 Loop Unrolling Degree Minimization for Periodic Register Allocation
Part 4: Epilog: Performance, Open Problems
Chapter 12 Statistical Performance Analysis: The Speedup-Test Protocol
Appendix 1: Presentation of the Benchmarks used in our Experiments
Appendix 2: Register Saturation Computation on Stand-alone DDG
Appendix 3: Efficiency of SIRA on the Benchmarks
Appendix 4: Efficiency of Non-Positive Circuit Elimination in the SIRA Framework
Appendix 5: Loop Unroll Degree Minimization: Experimental Results
Appendix 6: Experimental Efficiency of Software Data Preloading and Prefetching for Embedded VLIW
Appendix 7: Appendix of the Speedup-Test Protocol
